Yen-Chieh Huang

I am interested in building efficient computing systems, across machine learning systems, embedded systems, and hardware accelerators. Beyond that, I am also curious about intelligence itself — where it comes from, and what makes learning possible at all — which keeps me close to areas such as probabilistic modeling, information theory, and statistics.

I received my M.S. in Electrical Engineering from National Taiwan University in 2026, where I was fortunate to be advised by Prof. Pi-Cheng Hsiu and Prof. Ming-Syan Chen. Prior to that, I received my B.S. in Computer Science from National Yang Ming Chiao Tung University in 2024, where I did my undergraduate research with Prof. Tsung Tai Yeh.

I will be available for full-time positions starting in early 2027, after completing my mandatory military service. More details can be found in my CV. Feel free to reach out!

Selected publications

KV Admission: Learning What to Write for Efficient Long-Context LLM Inference

Yen-Chieh Huang, Pi-Cheng Hsiu, Rui Fang, and Ming-Syan Chen

To appear in Conference on Empirical Methods in Natural Language Processing (EMNLP), 2026

Abstract Paper Code

Long-context LLM inference is bottlenecked by the quadratic attention complexity and linear Key-Value (KV) cache growth. Prior approaches mitigate this via post-hoc selection or eviction but overlook the root inefficiency: indiscriminate token admission. In this paper, we formalize KV management as a causal system of three primitives: KV Admission, Selection, and Eviction. We instantiate KV Admission via Write-Gated KV (WG-KV), a lightweight mechanism that learns to predict token utility before cache entry. By filtering out redundant states early to maintain a compact global cache alongside a sliding local cache, WG-KV significantly reduces memory usage and accelerates both prefill and decode phases. Our results demonstrate that learning what to write is a principled and practical recipe for efficient long-context inference. Code is available at https://github.com/EMCLab-Sinica/WG-KV.
AQB8: Energy-Efficient Ray Tracing Accelerator through Multi-Level Quantization

Yen-Chieh Huang, Chen-Pin Yang, and Tsung Tai Yeh

In International Symposium on Computer Architecture (ISCA), 2025

Abstract Paper Code

Ray tracing (RT) is a rendering technique that produces high-fidelity images by simulating how light physically interacts with objects in a scene. This realism comes at a high computational and memory cost, largely driven by the need to find numerous ray-object intersections. To accelerate this process, scenes are typically structured using bounding volume hierarchy (BVH) trees, where objects are grouped within bounding boxes to minimize the number of required intersection tests. Specialized hardware, known as RT accelerators, accelerates BVH processing to boost computational speed, yet memory traffic persists as a major bottleneck, largely due to the bandwidth consumed by standard 32-bit floating-point (FP32) bounding boxes. Consequently, previous work has aimed to reduce memory traffic by compressing these boxes into low-bit (e.g., 8-bit) representations. However, existing compression techniques typically require decompressing bounding boxes back to FP32 for intersection tests, thus failing to eliminate the computational burden and energy cost associated with complex FP32 arithmetic during BVH traversal. This work introduces AQB8, an RT accelerator designed to operate on a quantized BVH tree constructed using a novel multi-level quantization technique. This approach enables RT to operate directly on low-bit integers using simpler, area-efficient hardware units, thereby drastically reducing the need for FP32 arithmetic during BVH traversal while mitigating overheads associated with reduced precision. As a result, across various scenes, AQB8 achieves a 70% reduction in DRAM accesses, a 49% reduction in energy consumption, a 27% hardware area reduction, and a 1.82x performance speedup over modern GPU RT accelerators. Our code is publicly available at https://github.com/nycu-caslab/AQB8.
Splitting Bottlenecks: Memory-Aware Neural Architecture Search for Multi-Branch TinyML

Chia-Yin Liu, Hashan Roshantha Mendis, Yen-Chieh Huang, Yi-Jung Chen, and Pi-Cheng Hsiu

To appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026

Abstract Video Code

Bringing modern intelligence to tiny devices is challenging because severe on-chip memory limits fundamentally constrain the multi-branch architectures prevalent in modern neural networks. Tensor splitting is a common technique to reduce peak memory usage. However, existing splitting strategies designed for single-branch networks fail to effectively reduce memory from retained tensors in multi-branch networks, where operator scheduling dominates the peak and splitting effectiveness varies widely across architectures.We present DupNAS, a framework that jointly optimizes neural architecture and multi-branch tensor splitting to enable higher-accuracy architectures under tighter memory constraints. In multi-branch networks, combinatorial operator schedules induce a vast splitting configuration space, making direct integration with neural architecture search intractable. DupNAS addresses this challenge by aggressively shrinking the configuration space without sacrificing peak memory optimality, while incrementally exploring configurations that resolve memory bottlenecks. We evaluate DupNAS across diverse vision models and memory constraints, as well as deploy the resulting networks on STM32 microcontrollers. By substantially reducing peak memory, DupNAS improves accuracy by 5 percentage points on average over existing splitting strategies at comparable optimization time, while achieving superior on-device accuracy-latency trade-offs.

Selected projects

Design and Implementation of a RISC CPU: From RTL to GDSII

Independently designed a 16-bit single-core CPU with a MIPS-like ISA and AXI4 interfaces for instruction and data memory, then carried it through the entire ASIC design flow from RTL to GDSII, covering logic synthesis, floorplanning, automatic place & route (APR), and final layout generation. Verified with RTL, gate-level, and post-layout simulation, plus STA, LVS, and DRC using industry-standard CAD tools.

Course Project, Integrated Circuit Design Laboratory (Prof. Chen-Yi Lee), NYCU, 2024

Source code is not publicly available due to course policy.
AQB8 Ray Tracing Accelerator: From Algorithm to FPGA and ASIC

Led the algorithm and hardware design behind our ISCA 2025 paper on AQB8, a ray tracing (RT) accelerator that replaces FP32 with low-bit integer arithmetic during BVH traversal. Prototyped it on a Xilinx Zynq FPGA with Vitis HLS, Vivado, and PetaLinux, then took the same design through a TSMC 40nm standard-cell ASIC flow with Catapult HLS, Design Compiler, QuestaSim, and PrimePower, for 49% lower energy and 27% less area than modern GPU RT accelerators.

Research Project, Computer Architecture System Laboratory (Prof. Tsung Tai Yeh), NYCU, 2025

Paper Code
Multimodal Perception and Comprehension of Corner Cases in Autonomous Driving

Led the team to 1st place (out of 12 teams) on multimodal understanding of autonomous driving corner cases. Enhanced LLaVA with LoRA fine-tuning plus cross-attention layers that fuse segmentation, instance, depth, and ViT features, enabling the model to reason over complex driving scenarios. Also built a self-critiquing augmentation loop where a frozen LLaVA compares the fine-tuned model's predictions with the ground truth and turns each missed detail into a new QA pair targeting the model's blind spots.

Course Team Project, Deep Learning for Computer Vision (Prof. Yu-Chiang Frank Wang), NTU, 2024

Poster Code

Misc

Away from work, I listen mostly to classical music, especially chamber music and orchestral works from the Romantics through the early twentieth century. I’m also drawn to exploring the fundamental nature of things, from the inner workings of computers to questions about intelligence, consciousness, and the meaning of life.